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never stop thinking. microcontrollers data sheet, v 1.0, oct. 2003 tc1910 32-bit single-chip microcontroller
edition 2003-10 published by infineon technologies ag, st.-martin-strasse 53, d-81541 mnchen, germany ? infineon technologies ag 2003. all rights reserved. attention please! the information herein is given to describe certain components and shall not be considered as warranted characteristics. terms of delivery and rights to technical change reserved. we hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. infineon technologies is an approved cecc manufacturer. information for further information on technology, delivery terms and conditions and prices please contact your nearest infineon technologies office in germany or our infineon technologies representatives worldwide (see address list). warnings due to technical requirements components may contain dangerous substances. for information on the types in question please contact your nearest infineon technologies office. infineon technologies components may only be used in life-support devices or systems with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
microcontrollers data sheet, v 1.0, oct. 2003 never stop thinking. tc1910 32-bit single-chip microcontroller
tc1910 preliminary revision history: 2003-10 v1.0 previous version: page subjects (major changes since last revision) we listen to your comments any information within this document that you feel is wrong, unclear or missing at all? your feedback will help us to continuously improve the quality of this document. please send your proposal (including a reference to this document) to: mcdocu.comments@infineon.com
tc1910 preliminary data sheet 1 v 1.0, 2003-10 tc1910 features the tc1910 offers a 32 bit tricore based microcontroller/dsp, which is mainly designed for automotive telematics applications. due to its high integration, this microcontroller/ dsp offers high system performance at minimized cost. typical telematics functions processed by risc-, dsp- and speech- (codec) modules are now combined in one component. this combination of dedicated speech peripherals (codec) and standard peripherals (ssc/spi, asc and iic), makes this microcontroller/dsp the engine tailored for a wide variety of telematics applications such as navigation, emergency call, speech interface or communication interface. ? tricore cpu/dsp with 4-stage pipeline: ? 66 mhz max. cpu clock frequency, 50 mhz max. fpi bus clock frequency. ? 32-bit super-scalar tricore main cpu ? 4-gbyte unified memory space support ? fast context-switching ? dual 16 x 16 multiply-accumulate (mac) unit ? 64-bit local memory bus (lmb) ? 32-bit flexible peripheral interface bus (fpi) ? 32-bit wide external bus unit (ebu) on-chip memories: ? 24 kbyte code scratch-pad ram (csram) ? 8 kbyte instruction cache (icache) ? 24 kbyte data scratch-pad ram (dsram) ? 8 kbyte data cache (dcache) ? 64 kbyte fast lmb sram ? 16 kbyte fpi sram (of which 8 kbyte stand-by sram) product specific peripherals: ? 14-bit double codec with flexible sample rates and fifo support ? 8 external interrupt inputs standard peripherals: ? 2 x asynchronous serial interface (asc) with irda-support ? 1 spi-compatible synchronous serial interface ? iic module ? 3 x 32 bit timer general peripherals: ? real time clock (rtc) ? watchdog timer (wdt) clock generation unit with pll debug support: ocds level 1 with jtag interface dual voltage supply (1.8v core, 3.3v i/o) power saving features -40c to +85c temperature range lbga-208 package
tc1910 data sheet 2 v 1.0, 2003-10 preliminary block diagram. figure 1 tc1910 device block diagram target applications bluetooth gateway (host for bt stack e.g. for handsfree with ec/nr or remote diagnostics) stand-alone speech human machine interface basic communication gateway digital audio processing (mp3 player, shock proof controller etc.) 32-bit flexible peripheral interface (fpi)bus tc1910 ocds debug/ jtag codec (iis) gptu port control sram 16kb rtc stm scu iic asc0 asc1 ssc tricore (tc1.3) cps dmu 24kb dsram 8kb dcache pmu 24kb csram 8kb icache 64-bit local memory bus (lmb) lfi bridge sram 64 kb ebu
tc1910 preliminary data sheet 3 v 1.0, 2003-10 logic symbol figure 2 tc1910 device logic symbol tc1910 gpio bypass xtal1 xtal2 xtal3 clkout xtal4 pll_ctrl v dd v ss v ddp v ddsb v ddpll v sspll v ddosc1 v ssosc1 port 1 8-bit port 0 8-bit port 2 16-bit port 3 16-bit 8 ocds/jtag control codec analog power supply v dd_cod0 nmi hdrst porst digital circuitry power supply oscillators pll general control test v ddosc2 v ssosc2 g pio /exix, codec bypass iic, ssc asc0 asc1 gptu v ss_cod0 v dd_cod1 v ss_cod1 v ref_cod v gnd_cod codec 0/1 10 external bus 83
tc1910 data sheet 4 v 1.0, 2003-10 preliminary pin configuration figure 3 tc1910 pinning lbga 208 v dd_ pwr v dd_ rtc ad30 a13 a17 bc3 mr/w cs2 cs6 bc0 hs10 brk in exin2 p1.7 exin1 p1.5 tdi gptu. 0 p1.4 p1.2 gptu. 7 asc1_ rx gptu. 6 gptu. 4 p2.1 exin0 p3.10 lrck exin6 tck p2.8 p2.2 gptu. 2 mute1 p2.9 exin5 p2.4 ssc_ mrst iic _ scl asc0_ tx asc0_ rx ssc_ sclk asc1_ tx exin7 p3.15 hrst ssc_ mtsr p2.0 pors t ao0- clk out p2.5 code c_dis exin4 by pass nmi ao1+ ai0- v agnd_ cod v dd_ pwr v dd _ guard cext v dd_ pll tm_ ctrl0 v ss _ pll ao1- v aref_ cod xtal2 v ddp_ pll ai0+ v ss_ gnd v ss_ gnd v ss_ gnd v ss_ gnd v ss_ gnd v ss_ gnd hs14 hs13 v dd_ pwr hs15 hs5 hs4 ad20 ad25 ad24 tm_ ctrl1 ad26 ad27 ad31 ad3 a20 a5 p2.3 ad17 ad13 ad9 ad21 ad22 ad19 ad8 ad18 ad16 ad12 ad7 ad15 ad14 ad6 ad5 ad11 ad10 a21 ebu clk ad1 a23 ad23 ad0 ad2 ad4 a19 bf clk0 a22 a16 a18 a12 a14 a15 a11 a8 a9 a10 v dd_ pwr a6 a7 cas a2 a4 a0 a3 a1 rd rd/wr bc2 bc1 cs5 ras cs4 cs3 cs1 cs0 wait baa csglb cs emu cs ovl cke adv cm delay ale hs12 hs11 hs6 hs8 hs9 hs7 brk out hs2 hs3 hs0 tms hs1 v dd_ pwr ocdse tdo p1.0 p1.3 p1.1 trst p1.6 mute0 v ddsb sclk exin3 scan mode gptu. 3 gptu. 5 gptu. 1 p3.11 iic _ sda v ssa_ cod0/1 ai1- ai1+ v dd_ cod0/1 ao0+ pllct rl_a0 v ss _ guard v dd_ osci v ssp _ pll v ddr xtal1 xtal4 xtal3 v ssa _32k ad29 ad28 v dd_ pwr2 v dd_ pwr2 v dd_ pwr2 v dd_ pwr2 top view a b c d f g h j k l m n p r t e a b c d e f g h j k l m n p r t 12345678910111213141516 12345678910111213141516
tc1910 preliminary data sheet 5 v 1.0, 2003-10 pin list table 0-1 pin definitions and functions symbol bga ball in/ out 1) functions ad0 ad1 ad2 ad3 ad4 ad5 ad6 ad7 ad8 ad9 ad10 ad11 ad12 ad13 ad14 ad15 ad16 ad17 ad18 ad19 ad20 ad21 ad22 ad23 ad24 ad25 ad26 ad27 ad28 ad29 ad30 ad31 h4 j2 h1 h3 h2 g1 g4 f1 e1 d1 g3 g2 f4 c1 f3 f2 e3 b1 e2 e4 a1 d2 d3 c2 c3 b2 a2 b3 a3 a4 b4 c4 i/o,s i/o,s i/o,s i/o,s i/o,s i/o,s i/o,s i/o,s i/o,s i/o,s i/o,s i/o,s i/o,s i/o,s i/o,s i/o,s i/o,s i/o,s i/o,s i/o,s i/o,s i/o,s i/o,s i/o,s i/o,s i/o,s i/o,s i/o,s i/o,s i/o,s i/o,s i/o,s external bus unit interface external address/data bus (multiplexed bus mode) or data bus (demultiplexed bus mode) for the ebu: ad0 address/data bus / data bus line 0 ad1 address/data bus / data bus line 1 ad2 address/data bus / data bus line 2 ad3 address/data bus / data bus line 3 ad4 address/data bus / data bus line 4 ad5 address/data bus / data bus line 5 ad6 address/data bus / data bus line 6 ad7 address/data bus / data bus line 7 ad8 address/data bus / data bus line 8 ad9 address/data bus / data bus line 9 ad10 address/data bus / data bus line 10 ad11 address/data bus / data bus line 11 ad12 address/data bus / data bus line 12 ad13 address/data bus / data bus line 13 ad14 address/data bus / data bus line 14 ad15 address/data bus / data bus line 15 ad16 address/data bus / data bus line 16 ad17 address/data bus / data bus line 17 ad18 address/data bus / data bus line 18 ad19 address/data bus / data bus line 19 ad20 address/data bus / data bus line 20 ad21 address/data bus / data bus line 21 ad22 address/data bus / data bus line 22 ad23 address/data bus / data bus line 23 ad24 address/data bus / data bus line 24 ad25 address/data bus / data bus line 25 ad26 address/data bus / data bus line 26 ad27 address/data bus / data bus line 27 ad28 address/data bus / data bus line 28 ad29 address/data bus / data bus line 29 ad30 address/data bus / data bus line 30 ad31 address/data bus / data bus line 31
tc1910 data sheet 6 v 1.0, 2003-10 preliminary a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 a17 a18 a19 a20 a21 a22 a23 cs0 cs1 cs2 cs3 cs4 cs5 cs6 csemu csovl r3 p4 t1 r2 r1 p3 p2 p1 n3 n2 n1 m4 m3 l4 m2 m1 l3 l1 l2 k4 k3 j4 k2 j3 r7 n7 p7 t6 r6 t5 p6 r8 t8 i/o,s i/o,s i/o,s i/o,s i/o,s i/o,s i/o,s i/o,s i/o,s i/o,s i/o,s i/o,s i/o,s i/o,s i/o,s i/o,s i/o,s i/o,s i/o,s i/o,s i/o,s i/o,s i/o,s i/o,s o,u o,u o,u o,u o,u o,u o,u o,u o,u external bus unit interface (continued) external address bus for the ebu or chip select output lines. a0 address bus line 0 a1 address bus line 1 a2 address bus line 2 a3 address bus line 3 a4 address bus line 4 a5 address bus line 5 a6 address bus line 6 a7 address bus line 7 a8 address bus line 8 a9 address bus line 9 a10 address bus line 10 a11 address bus line 11 a12 address bus line 12 a13 address bus line 13 a14 address bus line 14 a15 address bus line 15 a16 address bus line 16 a17 address bus line 17 a18 address bus line 18 a19 address bus line 19 a20 address bus line 20 a21 address bus line 21 a22 address bus line 22 a23 address bus line 23 cs0 chip select output 0 cs1 chip select output 1 cs2 chip select output 2 cs3 chip select output 3 cs4 chip select output 4 cs5 chip select output 5 cs6 chip select output 6 csemu chip select for emulator region csovl chip select for emulator overlay memory table 0-1 pin definitions and functions symbol bga ball in/ out 1) functions
tc1910 preliminary data sheet 7 v 1.0, 2003-10 rd rd/wr ale adv bc0 bc1 bc2 bc3 wait baa ebuclk bfclk0 csglb cmdelay mr/w cke ras cas r4 p5 r10 n9 n6 r5 t4 t3 t7 p8 j1 k1 n8 t9 r9 p9 n5 t2 i/o,u i/o,u o,d o,u i/o,u i/o,u i/o,u i/o,u i/o,u o,u o,u o,u o,u i,u o,u o,u o,u o,u external bus unit interface (continued) control bus for the ebu control lines. rd read control line rd/wr write control line ale address latch enable adv address valid output bc0 byte control line 0 bc1 byte control line 1 bc2 byte control line 2 bc3 byte control line 3 wait wait input baa burst address advance output ebuclk external bus clock bfclk0 additional clock c sglb chip select global c mdelay command delay mr/w motorola-style read/write cke clock enable r as row address strobe c as column address strobe p0 p0.0 p0.1 p0.2 p0.3 p0.4 p0.5 p0.6 p0.7 m14 m15 m16 l14 l15 k13 l16 k14 i/o i/o i/o i/o i/o i/o i/o i/o port 0 port 0 is an 8-bit general purpose i/o port, overlaid with codec digital signals and external interrupt inputs (p0.[3:0]). exi0in external interrupt input 0 exi1in external interrupt input 1 or data_in exi2in external interrupt input 2 or data_out exi3in external interrupt input 3 or mclk sclk lrck mute0 mute1 table 0-1 pin definitions and functions symbol bga ball in/ out 1) functions
tc1910 data sheet 8 v 1.0, 2003-10 preliminary p1 p1.0 p1.1 p1.2 p1.3 p1.4 p1.5 p1.6 p1.7 p14 r16 p15 p16 n14 n15 n16 m13 i/o i/o i/o i/o i/o i/o i/o i/o port 1 port 1 is a 8-bit bidirectional general purpose i/o port gpio only gpio only gpio only gpio only gpio only gpio only gpio only gpio only p2 p2.0 p2.1 p2.2 p2.3 p2.4 p2.5 p2.6 p2.7 p2.8 p2.9 p2.10 p2.11 p2.12 p2.13 p2.14 p2.15 a16 g13 g14 a15 f15 b15 e15 c15 f13 f14 d15 e14 d14 e13 c14 b14 i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o port 2 port 2 is a 16-bit bidirectional general purpose i/o port and input/output for serial interfaces (iic, asc0, ssc) gpio only gpio only gpio only gpio only gpio only gpio only scl iic serial port clock sda iic serial port data open drain gpio open drain gpio rxd0 asc0 receiver input/output txd0 asc0 transmitter output sclk ssc clock line mrst ssc master receive / slave transmit mtsr ssc master transmit / slave receive gpio/exi4in/pll_clc.loc k monitoring of the pll_clc.lock table 0-1 pin definitions and functions symbol bga ball in/ out 1) functions
tc1910 preliminary data sheet 9 v 1.0, 2003-10 p3 p3.0 p3.1 p3.2 p3.3 p3.4 p3.5 p3.6 p3.7 p3.8 p3.9 p3.10 p3.11 p3.12 p3.13 p3.14 p3.15 j13 k16 k15 j16 h13 h14 j15 h15 h16 d16 g16 e16 f16 g15 c16 b16 i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o port 3 port 3 is a 16-bit bidirectional general purpose i/o port which is also used as input/output for serial interfaces (asc1) and timer (gptu) gptu.0 gptu i/o line 0 gptu.1 gptu i/o line 1 gptu.2 gptu i/o line 2 gptu.3 gptu i/o line 3 gptu.4 gptu i/o line 4 gptu.5 gptu i/o line 5 gptu.6 gptu i/o line 6 gptu.7 gptu i/o line 7 rxd1 asc1 receiver input/output txd1 asc1 transmitter output gpio only gpio only / oscbyp latch-in input pin exi5in/ hwcfg0 latch-inexternal interrupt input 5 exi6in/ hwcfg1 latch-inexternal interrupt input 6 exi7in/ hwcfg2 latch-inexternal interrupt input 7 gpio only codec ai0+ ai0- ao0+ ao0- ai1+ ai1- ao1+ ao1- cext codec_dis d9 b9 c11 b12 c10 b10 b11 d11 d12 c12 i i o o i i o o i i codec codec 0 non-inverting input codec 0 inverting input codec 0 non-inverting output codec 0 inverting output codec 1 non-inverting input codec 1 inverting input codec 1 non-inverting output codec 1 inverting output codec external clock input codec disable (power saving) table 0-1 pin definitions and functions symbol bga ball in/ out 1) functions
tc1910 data sheet 10 v 1.0, 2003-10 preliminary debug trst tck tdi tdo tms ocdse brkin brkout t16 r15 t15 r14 p13 t14 r13 p12 i,d i,u i,u o i,u i,u i,u o debug (ocds/jtag control) reset/module enable jtag clock input serial data input serial data output state machine control signal ocds enable input ocds break input ocds break output test scan_mode pllctrl_ao tm_ctrl0 tm_ctrl1 j14 d8 c7 c5 i i i i test pins scan mode control current of different analog stages test mode control 0 test mode control 1 reserved pins hs0 hs1 hs2 hs3 hs4 hs5 hs6 hs7 hs8 hs9 hs10 hs11 hs12 hs13 hs14 hs15 n12 t13 r12 t12 j10 h10 p11 n11 r11 t11 p10 n10 t10 k9 k8 j7 io io io io io io io io io io io io io io io io reserved internal test and heat sink pins. must be routed as isolated pads on the pcb. heat sink 0 heat sink 1 heat sink 2 heat sink 3 heat sink 4 heat sink 5 heat sink 6 heat sink 7 heat sink 8 heat sink 9 heat sink 10 heat sink 11 heat sink 12 heat sink 13 heat sink 14 heat sink 15 bypass a12 i,d pll bypass control input nmi a13 i,u non-maskable interrupt input hrst b13 i/o,u bidirectional hardware reset table 0-1 pin definitions and functions symbol bga ball in/ out 1) functions
tc1910 preliminary data sheet 11 v 1.0, 2003-10 porst c13 i,u power-on reset input (must be active during power up) clkout a14 o cpu clock output xtal1 xtal2 a6 a7 i o pll/oscillator input/output xtal3 xtal4 d5 c6 i o real time clock oscillator input/output (32 khz) v aref_cod d10 - codec 0,1 reference voltage v agnd_cod c9 - codec 0,1 reference ground v dd_cod0/1 a10 - codec pad and analog power supply (3.3v) v ssa_cod0/1 a11 - codec pad and analog ground v dd_guard b8 - guard ring supply (1.8v) v ss_guard c8 - guard ring ground (1.8v) v dd_osci d7 - main oscilator power supply (1.8v) v dd_rtc a5 - rtc oscilator core supply (1.8v) v ssa_32k b5 - rtc and main osc. core ground (1.8v) v ddp_pll b6 - rtc and main osc. supply (3.3v) v ssp_pll b7 - rtc and main osc. ground (3.3v) v ddpll a9 - pll supply (1.8v) v sspll a8 - pll ground (1.8v) v ddr d6 - sram power supply (1.8v) v ddsb l13 - sram stand-by power supply (1.8v) v dd_pwr d4 d13 h7 n4 n13 - - - - - 3.3v power supply v dd_pwr2 g7 g10 k7 k10 - - - - 1.8v power supply table 0-1 pin definitions and functions symbol bga ball in/ out 1) functions
tc1910 data sheet 12 v 1.0, 2003-10 preliminary v ss_gnd g8 g9 h8 h9 j8 j9 - - - - - - digital power ground 1) the notification ?,u? after the input/output type defines an internal pull-up resistor. an internal pull-down resistor is indicated by ?,d?. for the lines ad[31:0] and a[23 :0], the type of the pull device can be selected ?s?. table 0-1 pin definitions and functions symbol bga ball in/ out 1) functions
tc1910 preliminary data sheet 13 v 1.0, 2003-10 system architecture and control 32-bit tricore cpu 32-bit architecture with 4-gbyte unified data, program and input/output address space fast automatic context-switch dual 16 x 16 multiply-accumulate (mac) unit saturating integer arithmetic register based design with multiple variable register banks bit handling packed data operations zero overhead loop precise exceptions flexible power management instruction set with high efficiency: 16/32-bit instructions for reduced code size little endian byte ordering with support for big and little endian byte ordering at bus interface boolean, array of bits, character, signed and unsigned integer, integer with saturation, signed fraction, double word integers and ieee-754 single precision floating-point data types bit, 8-bit byte, 16-bit half word, 32-bit word and 64-bit double word data formats powerful instruction set flexible and efficient addressing mode for high code density
tc1910 data sheet 14 v 1.0, 2003-10 preliminary on-chip code memories local memory bus memory (lmbram): address range of the 64 kbyte local memory bus memory: c000 0000 h - c000 ffff h (in segment 12 for cached operation) e800 0000 h - e800 ffff h (in segment 14 for non-cached operation) pmu scratch-pad sram (csram): the program memory unit (pmu) memory consists of 24-kbyte code scratchpad ram (csram) and 8-kbyte instruction cache (icache). address range of the csram: d400 0000 h - d400 5fff h on-chip data memories dmu scratch-pad sram (dsram): the data memory unit (dmu) memory consists of 24-kbyte data scratchpad ram (dsram) and 8-kbyte data cache (dcache). address range of the dsram: d000 0000 h - d000 5fff h fpi-bus data memory (fpidram): the fpi-bus data memory (fpidram) is a 16-kbyte static ram located on the fpi- bus. it contains two parts: fpidram0 and fpidram1. one half of it (fpidram1) can be used for standby power operation. address range of the fpi data memory: 9fff 8000 h - 9fff bfff h (in segment 9 for cached operation) bfff 8000 h - bfff bfff h (in segment 11 for non-cached operation)
tc1910 preliminary data sheet 15 v 1.0, 2003-10 system control unit (scu) the system control unit of the tc1910 basically handles all system control tasks. all these system functions are tightly coupled and therefore they are handled physically by one unit, the scu. the system tasks of the scu are: clock generation and control reset control power management control and wake-up watchdog timer device identification standby sram control external interrupt capability (8 sources) system timer (stm) the system timer is designed for global system timing applications requiring both high precision and long range. it is used by the cpu for softw are operating system issues. features: free-running 56-bit counter all 56 bits can be read synchronously different 32-bit portions of the 56-bit counter can be read synchronously driven by clock, f stm (normally identical with the system clock). counting begins at power-on reset continuous operation is not affected by any reset condition except power-on reset external bus interface (ebu_lmb) ebu_lmb is connected to the local memory bus (lmb) of the tc1910 and also to the fpi bus. ebu_lmb is always a slave on the lmb and a master/slave on the fpi bus. any lmb masters thus can access external memories or devices through ebu_lmb. currently the maximum length of the bursts are according to the size of program and data cache lines, i.e. 8 x 32-bit words. single transfers (non-burst) are supported for 8- bit, 16-bit and 32-bit wide access.
tc1910 data sheet 16 v 1.0, 2003-10 preliminary figure 4 ebu_lmb block diagram features supported in ebu_lmb: local memory bus (lmb 64-bit) support. external bus frequency: lmb frequency = 1:1 or 1:2 or 1:4. highly programmable access parameters. intel-style and motorola-sty le peripheral/device support. sdram support (burst access, multibanking, precharge, refresh). 16- and 32-bit sdram data bus and support of 64, 128 and 256mbit devices. burst flash support. multiplexed access (address & data on the same bus) when dram is not present on the external bus. data buffering: code prefetch buffer, read/write buffer. external master arbitration (compatible to c166 and other tricore devices). 8 programmable address regions (1 dedicated for emulator). little-endian and big-endian support. csglb signal, dedicated pin, bit programmable to combine one or more cs lines, for buffer control. rmw signal reflecting a read-modify-write action. signal for controlling data fl ow of slow-memory buffer. slave unit for external (off-chip) master to access devices on the fpi bus. master unit for fpi master to access external (off-chip) devices. data mover engine. sdram buffer xbc ebu_lmb xmi fpi bus 32-bit external bus 32-bit lmb bus 64-bit dme ebul3045_l external bus unit external master slower devices 50 mhz
tc1910 preliminary data sheet 17 v 1.0, 2003-10 interrupt system flexible interrupt prioritizing scheme with 256 interrupt priority levels fast interrupt response figure 5 block diagram interrupt system module c n service request nodes module a n service request nodes module b n service request nodes c pu interrupt arbitration bus module kernel module kernel module kernel 4 service request nodes 4 cpu interrupt control unit (icu) cpu core m ain interrupt control
tc1910 data sheet 18 v 1.0, 2003-10 preliminary fpi-bus the flexible peripheral interconnect bus is designed with the requirements of high- performance systems-on-chip in mind. key features: core independent multi-master capability demultiplexed operation clock synchronous peak transfer rate of up to 200 mbytes/s (@ 50 mhz bus clock) address and data bus scalable (32 bit address bus, 32 bit data bus ) 8-/16- and 32 bit data transfers broad range of transfer types from single to multiple data transfers burst transfer capability emi and power consumption minimized lmb-bus the local memory bus is a synchronous, pipelined, split bus with variable block size transfer support. all signals relate to the positive clock edge. the protocol supports 8,16,32 & 64 bits si ngle beat transactions and variable length 64 bits block transfers. key features: the lmb provides the following features: optimized for high speed and high performance 32 bit address, 64 bit data busses central simple per cycle arbitration slave controlled wait state insertion address pipelining (max depth - 2) split transactions variable block length - 2, 4 or 8 beats of 64 bit data
tc1910 preliminary data sheet 19 v 1.0, 2003-10 on-chip debug system (ocds) the tc1910 architecture is supporting ocds level 1. this means access to fpi bus and the whole fpi address space via the jtag interface pins. on-chip peripheral units the tc1910 offers several on-chip peripheral units such as serial controllers, timer units, and codec module. within the tc1910 all these peripheral units are connected to the tricore cpu/system via the fpi (flexible pe ripheral interconnect) bus. several io lines on the tc1910 ports are reserved for these peripheral units to communicate with the external world. peripheral units of the tc1910: three asynchronous/synchronous serial channels with baudrate generator, parity, framing and overrun error detecti on, irda mode, fifo buffers. one high speed synchronous serial channels with programmable data length and shift direction iic module one multi-functional general purpose timer units with three 32-bit timer/counter dual channel codec interface gpio blocks table 1 peripheral modules module address range i/o lines interrupt nodes asynchronous serial channel 0 (asc0) f000 0a00 h - f000 0aff h rdx0, tdx0 asc0_tsrc asc0_rsrc asc0_esrc asc0_tbsrc asynchronous serial channel 1 (asc1) f000 0b00 h - f000 0bff h rdx1, tdx1 asc1_tsrc asc1_rsrc asc1_esrc asc1_tbsrc synchronous serial channel (ssc) f000 0800 h - f000 08ff h sclk, mrst, mtsr ssc_tsrc ssc_rsrc ssc_esrc inter-ic bus (iic) f000 0500 h - f000 05ff h scl, sda iic_xp0src iic_xp1src iic_xp2src real time clock (rtc) f000 0100 h - f000 01ff h -rtc_src
tc1910 data sheet 20 v 1.0, 2003-10 preliminary system timer unit (stm) f000 0300 h - f000 03ff h -- general purpose timer (gptu) f000 0700 h - f000 07ff h gptu gptu_src0..7 speech interface (codec) f000 2400 h - f000 24ff h 2*2 analog in, 2*2 analog out, cext, codec_dis codec_src0..5 table 1 peripheral modules (cont?d) module address range i/o lines interrupt nodes
tc1910 preliminary data sheet 21 v 1.0, 2003-10 asynchronous/synchronous serial interfaces (asc 0/1) the asynchronous/synchronous serial interface asc provides serial communication between the tricore and other microcontrollers, microprocessors or external peripherals. features: full duplex asynchronous operating modes ? 8- or 9-bit data frames, lsb first ? parity bit generation/checking ? one or two stop bits ? baudrate from 3.125 mbaud to 0.74 baud (@ 50 mhz module clock) ? multiprocessor mode for automatic address/data byte detection ? loop-back capability half-duplex 8-bit synchronous operating mode ? baudrate from 6.25 mbaud to 637 baud (@ 50 mhz module clock) double buffered transmitter/receiver interrupt generation ? on a transmitter buffer empty condition ? on a transmit last bit of a frame condition ? on a receiver buffer full condition ? on an error condition (frame, parity, overrun error) support for irda automatic baudrate detection 8 byte fifo figure 6 general block diagram of the asc interface mca05253 clock control address decoder interrupt control f hw_clk asc module (kernel) port control rxd txd rxd txd tir tbir rir eir abstir abdetir
tc1910 data sheet 22 v 1.0, 2003-10 preliminary high-speed synchronous serial interface (ssc) the high speed synchronous serial interface ssc provides serial communication between microcontrollers, microprocessors or external peripherals. the ssc supports full-duplex and half-duplex synchronous communication up to 25 mbaud (@ 50 mhz module clock). the serial clock signal can be generated by the ssc itself (master mode) or be received from an external master (slave mode). data width, shift direction, clock polarity and phase are programmable. this allows communication with spi-compatible devices. transmission and reception of data are double-buffered. a 16-bit baud rate generator provides the ssc with a separate serial clock signal. features: master and slave mode operation ? full-duplex or half-duplex operation flexible data format ? programmable number of data bits : 2 to 16 bit ? programmable shift direction : lsb or msb shift first ? programmable clock polarity : idle low or high state for the shift clock ? programmable clock/data phase : data shift with leading or trailing edge of sclk maximum baudrate: 25 mbaud in master, 12.5 in slave mode (@ 50 mhz module clock) interrupt generation ? on a transmitter empty condition ? on a receiver full condition ? on an error condition (receive, phase, baudrate, transmit error) three pin interface figure 7 general block diagram of the ssc interface mcb04505_mod clock control address decoder interrupt control f hw_clk ssc module (kernel) port control mrst rxd txd master rxd txd slave slave master sclk mtsr sclk eir rir tir
tc1910 preliminary data sheet 23 v 1.0, 2003-10 inter-ic interface (iic) iic supports a certain protocol to allow devices to communicate directly with each other via two wires. one line is responsible for clock transfer and synchronization (scl), the other is responsible for the data transfer (sda). the on-chip iic bus module connects the pla tform buses to other external controllers and/or peripherals via the two-line serial iic interface. the iic bus module provides communication at data rates of up to 400 kbit/s and features 7-bit addressing as well as 10-bit addressing. this module is fully compatible to the iic bus protocol. the module can operate in three different modes: master mode , where the iic controls the bus trans actions and provides the clock signal. slave mode , where an external master controls the bus transactions and provides the clock signal. multimaster mode , where several masters can be connected to the bus, i.e. the iic can be master or slave. the on-chip iic bus module allows efficient communication via the common iic bus. the module unloads the cpu of low level tasks like: (de)serialization of bus data. generation of start and stop conditions. monitoring the bus lines in slave mode. evaluation of the device address in slave mode. bus access arbitration in multimaster mode. iic features: extended buffer allows up to 4 send/receive data bytes to be stored. selectable baud rate generation. support of standard 100 kbaud and extended 400 kbaud data rates. operation in 7-bit addressing mode or 10-bit addressing mode. flexible control via interrupt service routines or by polling.
tc1910 data sheet 24 v 1.0, 2003-10 preliminary timer unit (gptu) figure 8 shows a global view of all functional blocks of the gptu module. figure 8 general block diagram of the gptu interface the gptu consists of three 32-bit timers designed to solve such application tasks as event timing, event counting, and event recording. the gptu communicates with the external world via eight inputs and eight outputs. the three timers of the gptu module t0, t1, and t2, can operate independently from each other, or can be combined: general features: all timers are 32-bit precision timers with a maximum input frequency of f gptu /2. events generated in t0 or t1 can be used to trigger actions in t2 timer overflow or underflow in t2 can be used to clock either t0 or t1 t0 and t1 can be concatenated to form one 64-bit timer features of t0 and t1: each timer has a dedicated 32-bit reload register with automatic reload on overflow timers can be split into individual 8-, 16-, or 24-bit timers with individual reload registers overflow signals can be selected to generate service requests, pin output signals, and t2 trigger events two input pins can determine a count option mcb05052_modified clock control address decoder interrupt control sr1 sr2 f gptu sr3 sr0 gptu module (kernel) port control p0.1 / gpt1 sr7 sr6 sr5 sr4 in1 in2 in3 in0 in7 in6 in5 in4 out0 out1 out2 out3 out4 out5 out6 out7 io1 io7 io0 p0.0 / gpt0 io2 p0.2 / gpt2 io3 p0.3 / gpt3 p0.4 / gpt4 io4 io5 p0.5 / gpt5 io6 p0.6 / gpt6 p0.7 / g p t7
tc1910 preliminary data sheet 25 v 1.0, 2003-10 features of t2: optionally count up or down operating modes: ?timer ? counter ? incremental interface mode options: ? external start/stop, one-shot operat ion, timer clear on external event ? count direction control through software or an external event ? two 32-bit reload/capture registers reload modes: ? reload on overflow or underflow ? reload on external event: positive transition, negative transition, or both transitions capture modes: ? capture on external event: positive transition, negative transition, or both transitions ? capture and clear timer on external event: positive transition, negative transition, or both transitions can be split into two 16-bit counter/timers timer count, reload, capture, and trigger functions can be assigned to input pins. t0 and t1 overflow events can also be assigned to these functions. overflow and underflow signals can be used to trigger t0 and/or t1 and to toggle output pins t2 events are freely assignable to the service request nodes. real time clock unit rtc the real time clock (rtc) module is basically an independent timer chain and counts clock ticks. the base frequency of the rt c can be programmed via a reload counter. the rtc can work fully asynchronous to the system frequency and is optimized on low power consumption. features: the rtc serves different purposes: absolute system clock to dete rmine the current time and date cyclic time based interrupt alarm interrupt for wake up on a defined time 48-bit timer for long term measurements
tc1910 data sheet 26 v 1.0, 2003-10 preliminary codec interface the speech a/d and d/a converters (c alled codec) is designed for telephone and speech recognition quality. they can be us ed for microphone / earpiece applications. the tc1910 configuration implements a dual channel speech codec connected to the fpi bus. figure 9 general codec overview general purpose i/os (gpio) push/pull output drivers 3.3 volt operation for gpio programmable pull-up/-down devices at all pins optional open drain output mode clock control address decoder interrupt control sr1 sr2 f per sr3 sr0 codec module kernel v dd cod0 clock disable external clock input ai0+ ai0- ao0+ ao0- codec_dis cext sr4 sr5 v ss cod0 v dd cod1 v ss cod1 v ref cod v gnd cod ch0 non-inv. input ch0 inv. input ch0 non-inv. output ch0 inv. output ai1+ ai1- ao1+ ao1- ch1 non-inv. input ch1 inv. input ch1 non-inv. output ch1 inv. output mute0 mute1 mute channel 0 mute channel 1 iis si g nals codec bypass 5
tc1910 preliminary data sheet 27 v 1.0, 2003-10 id register table table 2 list of tc1910 id registers short name description address reset value scu_id scu identification register f000 0008 h 0019 c002 h manid manufacturer identification register f000 0070 h 0000 1820 h chipid chip identification register f000 0074 h 0000 8902 h rtid redesign tracing identification register f000 0078 h 0000 0000 h rtc_id rtc module identification register f000 0108 h 0000 5a04 h bcu_id bcu identification register f000 0208 h 0000 6a06 h stm_id system timer module identification register f000 0308 h 0000 c002 h jdp_id jtag/ocds module identification register f000 0408 h 0000 6305 h iic_id iic module identification register f000 0508 h 0000 4604 h gptu_id gptu module identification register f000 0708 h 0001 c002 h ssc_id ssc module identification register f000 0808 h 0000 4503 h asc0_id asc module identification register f000 0a08 h 0000 44e1 h asc1_id asc module identification register f000 0b08 h 0000 44e1 h codec_id codec identification register f000 2408 h 001c c002 h cps_id cpu module identification register f7e0 ff08 h 0015 c004 h cpu_id cpu identification register f7e1 fe18 h 000a c003 h ebu_id ebu_lmb module identification register f800 0008 h 0014 c003 h dmu_id dmu identification register f87f fc08 h 0008 c002 h pmu_id pmu module identification register f87f fd08 h 000b c002 h lcu_id lcu identification register f87f fe08 h 000f c003 h lfi_id lfi identification register f87f ff08 h 000c c003 h
tc1910 data sheet 28 v 1.0, 2003-10 preliminary power supply figure 10 shows the tc1910 power supply concep t, where certain logic modules are individually supplied with power. in this way, the noise margin is improved in the especially sensitive modules, like the a/d converter and the codec. figure 10 tc1910 power supply concept x y v dda v ssa codec 0 (analog) codec 1 (analog) battery backed stand- by sram adc (analog) pll (analog) all digital core components main osc v dda v ssa v dda v ssa v dda v ssa v dda v ssa v dd v ss v dd v ss v ddp v ssp v ddp v ssp rtc osc v dda v ssa v dd_sb v ddr v ss
tc1910 preliminary data sheet 29 v 1.0, 2003-10 power-up sequence during power-up reset pin porst has to be held active until both power supply voltages have reached at least their minimum values. during the power-up time (rising of the supply voltages from 0 to their regular operating values) it has to be ensured, that the core v dd power supply reaches its operating value first, and then the gpio v ddp power supply. during the rising time of the core voltage it must be ensured that 0< v dd -v ddp <0.5 v. during power-down, the core and gpio power supplies v dd and v ddp respectively, have to be switched off until all capacitances are discharged to zero, before the next power-up. note: the states of the pins are undefined when only the port voltage v ddp is on.
tc1910 data sheet 30 v 1.0, 2003-10 preliminary electrical characteristics parameter interpretation the parameters listed in the following partly represent the characteristics of the tc1910 and partly its demands on the system. to aid in interpreting the parameters right, when evaluating them for a design, they are marked in column ?symbol?: cc ( c ontroller c haracteristics): the logic of the tc1910 will provide signals with the respective characteristics. sr ( s ystem r equirement): the external system must provide signals with the respective characteristics to the tc1910.
tc1910 preliminary data sheet 31 v 1.0, 2003-10 absolute maximum ratings note: stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specific ation is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. during absolute maximum rating overload conditions ( v in > v dd or v in < v ss ) the voltage on v dd pins with respect to ground ( v ss ) must not exceed the values defined by the absolute maximum ratings. parameter symbol limit values unit notes min. max. ambient temperature t a -40 85 c under bias storage temperature t st -65 150 c junction temperature t j ? 125 c under bias voltage on i/o supply pins with respect to ground ( v ss ) v ddp -0.5 4.2 v voltage on core supply pins with respect to ground ( v ss ) v dd -0.3 2.1 v voltage on pll supply pins with respect to ground ( v ss ) v ddpll -0.3 2.1 v pll voltage between oscillator supply pins and ground ( v ss ). v ddosc -0.3 2.1 v voltage on any pin with respect to ground ( v ss ) v in -0.5 4.2 v input current on any pin during overload condition i ov -10 10 ma absolute sum of all input currents at overload condition i ov ? |100| ma power dissipation p diss ?1.0w
tc1910 data sheet 32 v 1.0, 2003-10 preliminary package parameters (p-lbga-208) operating conditions the following operating conditions must not be exceeded in order to ensure correct operation of the tc1910. all parameters specified in the following sections refer to these operating conditions, unless otherwise noted. parameter symbol limit values unit notes min. max. power dissipation p diss ?1.0w? thermal resistance r tha ? 30 k/w chip to ambient parameter symbol limit values unit notes min. max. supply voltage v ddp 3.0 3.6 1) 1) voltage overshoot to 4 v is permissible, provided the pulse duration is less than 100 s and the cumulated summary of the pulses does not exceed 1 h v i/o supply v dd 1.71 1.89 2) 2) voltage overshoot to 2 v is permissible, provided the pulse duration is less than 100 s and the cumulated summary of the pulses does not exceed 1 h v core supply v ddpll 1.71 1.89 v pll supply v ddosc 1.71 1.89 v oscillator supply ground voltage v ss 0v input current on any pin during overload condition i ov -5 5 ma v ov > v ddp + 0.3v v ov < v ss - 0.3v absolute sum of all input currents at overload condition | i ov | ?|50|ma ambient temperature under bias t a -40 85 c cpu clock f cpu ?66mhz external load capacitance c l ?50pf
tc1910 preliminary data sheet 33 v 1.0, 2003-10 dc characteristics gpio pins parameter symbol limit values unit test conditions min. max. output low voltage (strong driver) v ol -1 0.4 vi ol = 10 ma i ol = 2.5 ma output high voltage (strong driver) v oh 2.4 - v i oh = - 2.5 ma output low voltage (medium driver) 1) 1) not subject to production test, veri fied by design/characterization. v ol -0.4vi ol = 1 ma output high voltage (medium driver) 1) v oh 2.4 - v i oh = - 1 ma output low voltage (weak driver) 1) v ol -0.4vi ol = 100 a output high voltage (weak driver) 1) v oh 2.4 - v i oh = - 100 a input low voltage v il -0.3 0.8 v lvttl input high voltage v ih 2.0 v ddp +0.3 or 3.7v v whatever is lower input leakage current i oz1 - 500 na 0v< v in < v ddp pull-up current 2) 2) the maximum current that may be drawn while the respective signal line remains inactive. |i puh | - 1 a v out = 2.0v pull-up current 3) 3) the minimum current that must be drawn in order to drive the respective signal line active. |i pul | 20 - a v out = 0.8v pull-down current |i pdl | - 0.8 a v out = 0.8v pull-down current |i pdh | 20 - a v out = 2.0v pin capacitance 1) c io - 10 pf f = 1mhz @ t a = 25 o c
tc1910 data sheet 34 v 1.0, 2003-10 preliminary nmi pin nmi pin is an input pin with different pull-up characteristics than other pins. the related characteristics are given in the following table note: nmi pin does not have a pull-down device. oscillator pins parameter symbol limit values unit test conditions min. max. max. current allowed through the pull-up device while pin (input) voltage remains still at the high level |i puh |- 4 uav out =2.0v min. current needed through the pull-up device so that pin voltage is driven to the low level. |i pul |100 - uav out =0.8v parameter symbol limit values unit test conditions min. max. input leakage current (analog input) at xtal1 1) 1) only applicable in deep sleep mode i oz1 cc - 200 na 0v< v in < v ddp input low voltage xtal1 v ilx sr -0.3 v- input high voltage xtal1 2) 2) not subject to production test, veri fied by design/characterization. v ihx sr 0.8 v dd -0.3 v dd -0.35 v dd -0.4 v dd -0.43 vf osc =4mhz f osc =8mhz f osc =12mhz f osc =16mhz xtal1 input current i ix1 cc - 20 a 0v < v in < v dd xtal3 input current 2) i ix3 cc - 0.5 a 0v < v in < v dd
tc1910 preliminary data sheet 35 v 1.0, 2003-10 iic pins each iic pin is an open drain output pin with different characteristics than other pins. the related characteristics are given in the following table note: no 5 v iic interface is supported wit h these pads. only voltages lower than 3.60 v must be applied to these pads. note: iic pins have no pull-up and pull-down devices. parameter symbol limit values unit test conditions min. max. output low voltage v ol cc -0.4 0.6 v3 ma 6 ma input high voltage 1) v ih sr 0.7v ddp 3.6 v - input low voltage 1) v il sr -0.3 0.3v ddp v- input leakage current i oz2 cc - + - 500 na pin capacitance 1) 1) not subject to production test, veri fied by design/characterization. c io cc - 10 pf f=1mhz@ t a =25 o c
tc1910 data sheet 36 v 1.0, 2003-10 preliminary codec electrical characteristics parameter symbol limit values unit test conditions min. typ. max. digital supply voltage v dd 1.71 1.8 1.89 v analog supply voltage v dda 3.0 3.3 3.6 v analog supply ground v ssa -0.1 0.0 +0.1 v external reference voltage v aref 1) 1) reference voltage outside the nominal range causes reduced dynamic range, decreased distortion/clipping margins, increased/decreased gain. 1.14 1.2 +1.26 2) 2) v ssa =v agnd =0v v analog reference ground v agnd v ssa - 0.05 v ssa v ssa + 0.05 v analog input voltage (rms) v ain 0.775 v rms 3) 3) please take the gain settings of the analog preamplifier into account, therefore v imaxreal =v imax /gain analog output voltage (rms) v aout 0.775 v rms input resistace of the analog inputs 4) 4) simulation value. rain - 30 - kohm differential input, gain: -12,-6, 0 db - 15 - kohm single-ended input, gain: -12,-6, 0 db - 60 - kohm differential input, gain: 6 to 30 db - 30 - kohm single-ended input, gain: 6 to 30 db internal reference voltage vref (bandgap voltage) 5) 5) for external usage, bandgap reference voltage is strongly dependent on the external load (<500 mohm). in this case, high impedance buffer must be used. v bgp 1.1 1.2 1.3 v agccr. bgpsel[1,0] =00
tc1910 preliminary data sheet 37 v 1.0, 2003-10 codec adc and dac path characteristics note: numbers without units in the test conditions column are relative frequency values to the chosen sampling frequency. e.g. 0.425 equals 3.4 khz @ 8 khz sampling frequency. parameters min. typ. max. unit test conditions 1) 1) values given in this table are valid for all sampling frequencies. attenuation distortion (ref. freq. 1014 hz) (ref. level 0dbm0) 2) 2) 0dbm0 is equivalent to -12dbm is equal to 194.7 mv rms. 0 -0.25 -0.25 -0.25 0 0.25 0.45 db db db db db < 0.025 0.025-0.0375 0.0375-0.3 0.3-0.425 > 0.425 signal to total distor- tion -55 -45 db at 0dbm0 gain tracking (ref. freq. 1014 hz) (ref. level 0dbm0) 2) -0.3 -0.6 -1.6 0.3 0.6 1.6 db db db +3 to -40 dbm0 -40 to -50 dbm0 -50 to -55 dbm0 idle channel noise -80 -75 dbm 0 receive &transmit cross talk -80 -75 db harmonic distortion -60 -50 db at 0dbm0 gain (ref. freq. 1014 hz) (ref. level 0dbm0) 2) -0.8 0 0.8 db receive &transmit power supply rejection ratio (psrr) --60 -40 -35 -35 db db receive (0.0375-0.425) 3) transmit(0.0375-0.425) 3) 3) supply ripple 70 mv.
tc1910 data sheet 38 v 1.0, 2003-10 preliminary power supply current note: the power supply current values refer to the total current at 1.8v power supply, at lmb/fpi bus frequency ratio of 2:1, while running an average application. these numbers are estimation based on average device measurements. parameter symbol limit values unit test conditions typ. 1) 1) typical values are measured at 25c, cpu clock at 66 mhz and nominal supply voltage, i.e. 3.3v for v ddp and 1.8v for v dd , v ddpll , v ddosc max. active mode supply current i dd 180 ? ma sum of all i dd . idle mode supply current i id 90 ? ma at 1.8v core supply deep sleep mode supply current i ds 0.25 ? ma at 1.8v core supply
tc1910 preliminary data sheet 39 v 1.0, 2003-10 ac characteristics operating conditions apply. output rise/fall times gpio pins rise/fall time measurements are made between 10% and 90%. the following table is valid for the gpio pins pad drivers. output pad characteristics are controllable via drvctrx registers. pad modus rise / fall time symbol limit values temp comp unit test conditions min. max. strong driver sharp edge medium edge 1) soft edge 1) 1) not subject to production test, veri fied by design/characterization. sf sm ss - - - 3 6 12 yes yes yes ns ns ns @50pf @50pf @50pf
tc1910 data sheet 40 v 1.0, 2003-10 preliminary timing characteristics (operating conditions apply) note: timing parameters are not subject to production test, they are verified by design/ characterization. figure 11 input/output waveforms for ac tests - for gpio, dedicated and ebu pins mct04880 2.4v 0.4v 2.0v 0.8v 2.0v 0.8v test p oints ac inputs during testing are driven at 2.4v for a logic ?1? and 0.4v for a logic ?0?. timing measurements are made at v ihmin for a logic ?1? and v ilmax for a logic ?0?.
tc1910 preliminary data sheet 41 v 1.0, 2003-10 external oscillator at xtal1 timing requirements (operating conditions apply) figure 12 external clock at xtal1 requirements note: v ddosc , v ihx and v ihl are defined in the oscillator pins dc characteristics chapter. note: it is strongly recommended to meas ure the oscillation allowance (negative resistance) in the final target system (l ayout) to determine the optimal parameters for the oscillator operation. please refer to the limits specified by the crystal supplier. parameter symbol limits unit min. max. main oscillator xtal frequency 1) 1) oscillator bypass pin p3.11 latch-in value high. internal oscillator provides the input clock signal. with/without pll f osc sr 4 16 mhz frequency of an external oscillator driving at xtal1 2) 2) oscillator bypass pin p3.11 latch-in value low. internal oscillator disabled. external oscillator provides the input clock signal. with pll 3) without pll 4) 3) internal pll provides the system clock. bypass pin latch-in value low. pll prescaler value p=1. 4) internal pll bypassed. bypass pin latch-in value high. external oscillator provides the system clock directly. when codec modules is active its frequency limitations must be taken into consideration. otherwise, minimum frequency in this mode can go as low as zero. f oscdd sr 4 - 25 25 mhz input clock high time t 1 sr 16 ? ns input clock low time t 2 sr 16 ? ns input clock rise time t 3 sr ? 7ns input clock fall time t 4 sr ? 7ns mct04882 0.5 v ddosc input clock at xtal1 t osc t 1 t 2 v il x v ih x t 4 t 3
tc1910 data sheet 42 v 1.0, 2003-10 preliminary cpu clock timing (operating conditions apply; c l = 50 pf) figure 13 clkout timing parameter symbol limits unit min. max. clkout period t clkout cc 15 ? ns clkout high time t 1 cc 6 ? ns clkout low time t 2 cc 6 ? ns clkout rise time t 3 cc ? 3ns clkout fall time t 4 cc ? 3ns 0.9 v dd mct04883 0.5 v dd clkout t cpuclk t 1 t 2 0.1 v dd t 4 t 3
tc1910 preliminary data sheet 43 v 1.0, 2003-10 pll parameters note: when tc1910 starts-up with the pll not bypassed, first user instructions are executed with the frequency defined by the vco free-running frequency ( f pllbase ) and by the reset value of the pll_clc register (the k-divider and vcosel bitfields). it is software responsibility to initialize its own appropriate values in the bitfields in this register, before giving the command for the vco to lock to the input frequency. for more information, see the users manual, system units, system control unit chapter. parameter symbol limit values 1) 1) not subject to production test, veri fied by design/characterization. unit min. max. accumulated jitter d n see figure 14 ? vco frequency range f vco 100 150 2) 2) @ vcosel = ?00? mhz 150 200 3) 3) @ vcosel = ?01? mhz 200 250 4) 4) @ vcosel = ?10? mhz 250 300 5) 5) @ vcosel = ?11? mhz pll base frequency f pllbase 20 80 2) mhz 20 130 3) mhz 20 180 4) mhz 20 230 5) mhz pll lock-in time t l ? 200 s
tc1910 data sheet 44 v 1.0, 2003-10 preliminary figure 14 approximated maximum accumulated pll jitter the following two formulas define the (absolute) approximate maximum value of jitter d n in [ns] dependent on the k-factor, the system clock frequency f sys in [mhz], and the number p of consecutive f sys periods. [1] [2] with rising number p of clock cycles the maximum jitter increases linearly up to a specific value of p . beyond this value of p the maximum accumulated jitter remains at a constant value. tc191x_pll_jitter 0 0.0 p ns d n 1.0 2.0 3.0 5.0 510 15 20 25 30 4.0 35 d n p k = max. jitter = number of consecutive f sys periods = k-divider of pll f sys = 60 mhz ( k = 5) f sys = 50 mhz ( k = 6) f sys = 40 mhz ( k = 7) f sys = 33 mhz ( k = 8) f sys = 66 mhz ( k = 4) for p < 0.25 f sys d n [ns] = [( 735 f sys k + 0.9) p f sys 0.25 + 0.5 ] for p > d n [ns] = [ 0.25 f sys 735 f sys k + 1.4 ]
tc1910 preliminary data sheet 45 v 1.0, 2003-10 timing for ebu_lmb clock outputs (operating conditions apply; c l = 50 pf) figure 15 ebu_lmb clock output timing parameter symbol limits unit min. max. ebuclk period t 1 cc 15 ? ns ebuclk high time t 2 cc 6 ? ns ebuclk low time t 3 cc 6 ? ns ebuclk rise time t 4 cc ? 2.5 ns ebuclk fall time t 5 cc ? 2.5 ns bfclk0 period t 6 cc 20 ? ns bfclk0 high time t 7 cc 9 ? ns bfclk0 low time t 8 cc 9 ? ns bfclk0 rise time t 9 cc ? 3.5 ns bfclk0 fall time t 10 cc ? 2.5 ns 0.9 v dd mct04884 0.5 v dd ebuclk/ bfclk0 t 1 (t 6 ) t 2 (t 7 ) 0.1 v dd t 3 (t 8 ) t 5 (t 10 ) t 4 (t 9 )
tc1910 data sheet 46 v 1.0, 2003-10 preliminary timing for sdram access signals (operating conditions apply; c l = 50 pf) parameter symbol limits unit min. max. cke high from ebuclk t 1 cc - 7.0 ns cke low from ebuclk t 2 cc 2.0 - ns a(23:0) output valid from ebuclk t 3 cc - 7.0 ns a(23:0) output hold from ebuclk t 4 cc 2.0 - ns cs(6:0) low from ebuclk t 5 cc - 7.0 ns cs(6:0) high from ebuclk t 6 cc 2.0 - ns ras low from ebuclk t 7 cc - 7.0 ns ras high from ebuclk t 8 cc 2.0 - ns cas low from ebuclk t 9 cc - 7.0 ns cas high from ebuclk t 10 cc 2.0 - ns rd/wr low from ebuclk t 11 cc - 7.0 ns rd/wr high from ebuclk t 12 cc 2.0 - ns bc(3:0) low from ebuclk t 13 cc - 7.0 ns bc(3:0) high from ebuclk t 14 cc 2.0 - ns ad(31:0) output valid from ebuclk t 15 cc - 7.7 ns ad(31:0) output hold from ebuclk t 16 cc 2.0 - ns ad(31:0) input setup to ebuclk t 17 sr 2.0 - ns ad(31:0) input hold from ebuclk t 18 sr 4.0 - ns
tc1910 preliminary data sheet 47 v 1.0, 2003-10 figure 16 sdram access timing mct05319 column row column row data (n-1) data (0) ebuclk cke a(23:0) csx ras cas t 1 write access: t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 10 t 11 t 12 t 13 t 14 t 15 t 16 rd/wr bc(3:0) ad(31:0) ebuclk cke a(23:0) csx ras cas read access: t 3 t 4 t 6 t 10 rd/wr bc(3:0) ad(31:0) data (0) data (n-1) t 2 t 9 t 13 t 14 t 17 t 18
tc1910 data sheet 48 v 1.0, 2003-10 preliminary timing for burst flash access signals operating conditions apply; c l = 50 pf) parameter symbol limits unit min. max. a(23:0) output valid from bfclk0 t 1 cc ? 11.0 ns a(23:0) output hold from bfclk0 t 2 cc 0.0 ? ns cs(6:0) low from bfclk0 t 3 cc ? 9.0 ns adv low from bfclk0 t 5 cc ? 10.0 ns adv high from bfclk0 t 6 cc 3.0 ? ns baa low from bfclk0 t 7 cc ? 10.0 ns baa high from bfclk0 t 8 cc 3.0 ? ns rd low from bfclk0 t 9 cc ? 10.0 ns ad(31:0) input setup to bfclk0 t 11 sr 6.0 ? ns ad(31:0) input hold from bfclk0 t 12 sr 3.0 ? ns
tc1910 preliminary data sheet 49 v 1.0, 2003-10 figure 17 burst flash access timing (instruction read) address valid valid valid bfclk0 t 1 t 5 t 6 t 3 t 9 t 7 t 8 t 12 t 11 a[23:0] rd baa adv d[31:0] note: between the end of the address phase (adv goes high) and the beginning of the command phase (rd goes low) several cycles of command delay phase can be inserted. csx t 2 mct04889_mod_la
tc1910 data sheet 50 v 1.0, 2003-10 preliminary timing for demultiplexed access signals 1) (operating conditions apply; c l = 50 pf) 1) it is user responsibility to program an appropriate whole number of clock cycles to generate the correct phase length according to the particular asynchronous memory/peripheral device specification. parameter symbol limits unit min. max. ale low from ebuclk t 1 cc ? 8.0 ns ale high from ebuclk t 2 cc 2.0 ? ns a(23:0) output valid from ebuclk t 3 cc ? 8.0 ns a(23:0) output hold from ebuclk t 4 cc 2.0 ? ns cs(6:0) low from ebuclk t 5 cc ? 8.0 ns cs(6:0) high from ebuclk t 6 cc 2.0 ? ns mr/w low from ebuclk t 7 cc ? 8.0 ns mr/w high from ebuclk t 8 cc 2.0 ? ns rmw low from ebuclk t 9 cc ? 8.0 ns rmw high from ebuclk t 10 cc 1.0 ? ns rd low from ebuclk t 11 cc ? 8.0 ns rd high from ebuclk t 12 cc 0.0 ? ns rd/wr low from ebuclk t 13 cc ? 8.0 ns rd/wr high from ebuclk t 14 cc 2.0 ns cmdelay input setup to ebuclk t 15 sr 4.0 ? ns cmdelay hold from ebuclk t 16 sr 3.0 ? ns wait input setup to ebuclk t 17 sr 4.0 ? ns wait hold from ebuclk t 18 sr 3.0 ? ns bc(3:0) low from ebuclk t 19 cc ? 8.0 ns bc(3:0) high from ebuclk t 20 cc 2.0 ? ns ad(31:0) output valid from ebuclk t 21 cc ? 8.0 ns ad(31:0) output hold from ebuclk t 22 cc 0.0 ? ns ad(31:0) input setup to ebuclk t 23 sr 4.0 ? ns ad(31:0) input hold from ebuclk t 24 sr 4.0 ? ns
tc1910 preliminary data sheet 51 v 1.0, 2003-10 figure 18 demultiplexed write access address mct05320 ebuclk t 1 t 2 t 3 t 4 t 6 t 5 t 7 t 14 ale a(23:0) csx mr/w rd/wr cmdelay t 15 t 16 wait t 17 t 18 t 19 bc(3:0) t 20 t 13 t 20 t 19 data out t 21 t 22 ad(31:0)
tc1910 data sheet 52 v 1.0, 2003-10 preliminary figure 19 demultiplexed read access address mct05321 ebuclk t 1 t 2 t 3 t 4 t 6 t 5 t 8 ale a(23:0) csx mr/w rd cmdelay wait t 17 t 18 t 19 bc(3:0) t 11 t 20 t 19 data t 24 ad(31:0) rmw t 9 t 10 t 12 t 15 t 16 t 23 note: rmw signal is available only during read-modify-write access.
tc1910 preliminary data sheet 53 v 1.0, 2003-10 timing for multiplexed access signals 1) (operating conditions apply; c l = 50 pf) 1) it is user responsibility to program an appropriate whole number of clock cycles to generate the correct phase length according to the particular asynchronous memory/peripheral device specification. parameter symbol limits unit min. max. ale high from ebuclk t 1 cc ? 8.0 ns ale low from ebuclk t 2 cc 2.0 ? ns ad(31:0) output valid from ebuclk t 3 cc ? 8.0 ns ad(31:0) output hold from ebuclk t 4 cc 0.0 ? ns ad(31:0) input setup to ebuclk t 5 sr 4.0 ? ns ad(31:0) input hold from ebuclk t 6 sr 4.0 ? ns cs(6:0) low from ebuclk t 7 cc ? 8.0 ns cs(6:0) high from ebuclk t 8 cc 1.0 ? ns mr/w low from ebuclk t 9 cc ? 8.0 ns mr/w high from ebuclk t 10 cc 2.0 ? ns rmw low from ebuclk t 11 cc ? 8.0 ns rmw high from ebuclk t 12 cc 1.0 ? ns rd/wr low from ebuclk t 13 cc ? 8.0 ns rd/wr high from ebuclk t 14 cc 2.0 ? ns rd low from ebuclk t 15 cc ? 8.0 ns rd high from ebuclk t 16 cc 0.0 ? ns cmdelay input setup to ebuclk t 17 sr 4.0 ? ns cmdelay hold from ebuclk t 18 sr 3.0 ? ns wait input setup to ebuclk t 19 sr 4.0 ? ns wait hold from ebuclk t 20 sr 3.0 ? ns bc(3:0) low from ebuclk t 21 cc ? 8.0 ns bc(3:0) high from ebuclk t 22 cc 2.0 ? ns
tc1910 data sheet 54 v 1.0, 2003-10 preliminary figure 20 multiplexed write access address mct05322 ebuclk t 1 t 2 t 3 t 4 t 8 t 7 t 9 t 14 ale ad(31:0) csx mr/w rd/wr cmdelay t 17 t 18 wait t 19 t 20 bc(3:0) t 22 t 13 t 22 t 21 data t 4 t 3 t 21
tc1910 preliminary data sheet 55 v 1.0, 2003-10 figure 21 multiplexed read access address ebuclk t 1 t 2 t 3 t 6 t 8 ale ad(31:0) csx data t 4 t 5 mct05323 t 8 t 7 t 10 csx mr/w rd cmdelay wait t 19 t 20 t 21 bc(3:0) t 15 t 22 t 21 rmw t 11 t 12 t 16 t 17 t 18 note: rmw signal is only available during read-modify-write access.
tc1910 data sheet 56 v 1.0, 2003-10 preliminary timing for external bus arbitration signals (operating conditions apply; c l = 50 pf) note: the signals hold , hlda and breq are alternate function of the cs5 , cs6 and csovl pins. parameter symbol limits unit min. max. hold input setup to ebuclk t 1 sr 6.0 ? ns hold input hold from ebuclk t 2 sr 8.0 ? ns hlda low from ebuclk t 3 cc ? 10.0 ns hlda high from ebuclk t 4 cc ? 9.0 ns hlda input setup to ebuclk t 5 sr 8.0 ? ns hlda input hold from ebuclk t 6 sr 8.0 ? ns breq low from ebuclk t 7 cc ? 10.0 ns breq high from ebuclk t 8 cc ? 9.0 ns
tc1910 preliminary data sheet 57 v 1.0, 2003-10 figure 22 external bus arbitration timing m ct05324_mod ebuclk hold hlda breq t 1 t 2 t 4 t 3 t 8 t 7 external master mode ebuclk breq hlda hold t 7 t 8 t 6 t 5 t 2 external slave mode t 1
tc1910 data sheet 58 v 1.0, 2003-10 preliminary ssc master mode timing (operating conditions apply; c l = 50 pf) figure 23 ssc master mode timing parameter symbol limit values unit min. max. sclk period t sclk cc 40 ns mtsr low/high from sclk edge t 5 cc - 2.0 ns mrst setup to sclk edge t 6 sr 15 - ns mrst hold from sclk edge t 7 sr 15 - ns 0.9 v dd mct04885 0.5 v dd sclk t sclk 0.1 v dd t 4 t 3 0.9 v dd 0.5 v dd 0.1 v dd t 4 t 3 (con.po,con.ph=00 or 11) sclk (con.po,con.ph=01 or 10) t 5 state n-1 state n state n+1 data valid data valid t 6 t 7 mtsr mrst t 2 t 2
tc1910 preliminary data sheet 59 v 1.0, 2003-10 package outlines figure 24 p-lbga-208 package you can find all of our packages, sorts of packing and other in our infineon internet page ?products?: http://www.infineon.com/products
tc1910 data sheet 60 v 1.0, 2003-10 preliminary
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